TSMC Unveils A13 Chip Process, Skips Costly EUV Tools for Future Growth
Taiwan Semiconductor Manufacturing Company introduced a new lineup of chip technologies during its 2026 North America Technology Symposium. At the same time, the company confirmed it does not plan to adopt next-generation high numerical aperture EUV lithography machines from ASML in the near future.
At the event in Santa Clara, California, it unveiled A13, a direct shrink of the A14 node that delivers 6% area savings while remaining fully backward-compatible. Meanwhile, A13 is scheduled for production in 2029, just one year after A14. In addition, the company introduced N2U, a derivative of its 2nm platform that offers 3–4% speed gains or 8–10% power reduction, with production planned for 2028.
Furthermore, a separate enhancement called A12, featuring backside power delivery, will also enter production in 2029. However, the decision to avoid high-NA EUV tools, which cost about $380 million each, has already influenced market sentiment. As a result, shares of ASML fell roughly 3.7% following the announcement.
Focus Shifts to Advanced Packaging
Instead of relying on costly lithography tools, the company is prioritizing advanced multi-chip packaging to drive performance gains. According to senior vice president Kevin Zhang, the research team continues to push scaling limits without adopting high-NA systems. “They continue to find a way to drive technology scaling without using high-NA,” Zhang said. “One day, they may have to use it, but at this point, given the technology, with A14, A13, we continue to be able to harvest the benefits from current EUV, and not have to go to high-NA, which is very expensive”.
Moreover, the company is expanding its CoWoS packaging capabilities. It currently produces 5.5-reticle-size packages, and it plans to scale to 14-reticle-size versions by 2028. These advanced packages could integrate around 10 large compute dies and 20 HBM stacks. Looking further ahead, a 40-reticle system-on-wafer technology is expected in 2029.
Industry experts see this as a broader shift in chip design strategy. Dan Hutcheson of TechInsights noted the significance of this transition. “Advanced packaging is displacing lithography as the key enabler of density gains,” he said.
Implications for the Chip Industry
Although the company is avoiding high-NA EUV for now, demand for these machines has not disappeared. For example, Intel has already adopted the technology. Meanwhile, ASML expects to ship between five and ten systems in 2026, with annual shipments exceeding 20 by 2028.
Additionally, memory manufacturers like SK Hynix and Samsung are likely customers. However, since this manufacturer produces more than half of the world’s advanced chips, its strategy significantly shapes market demand. Consequently, extending the use of existing EUV tools through at least 2029 limits near-term opportunities for high-NA systems.
Still, future adoption remains possible. Observers suggest that a sub-1nm node targeted for trial production in 2029 could mark the first use of high-NA EUV. For now, however, the company is betting that stacking more silicon within advanced packages will outperform shrinking transistors with increasingly expensive tools.
