In a tight battle to create the most cutting-edge semiconductors in the world, Samsung said that it has started mass producing 3-nanometer circuits. Taiwan Semiconductor Manufacturing Co. (TSMC) was the closest competitor at the time. The company claimed that compared to 5-nanometer processors, its new chips’ so-called Gate-All-Around transistor architecture will effectively cut power consumption by up to 45 percent while boosting performance by 23 percent.
Next-generation technologies
Samsung will also use something called Multi-Bridge-Channel FET (MBCFET™). Implemented for the first time ever, this process defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET™,” said in the statement Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.
“We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”
The firm also has plans to expand to mobile processors. Meanwhile, TSMC has said its 3-nanometer mass production will commence in the second half of the year, far later than Samsung. Does this mean that Samsung will win the competition for large multiyear orders from the likes of Apple and Qualcomm?
TSMC currently dominates the market for contract chip production and is the manufacturer of Apple’s chips for its iPhones, iPads, MacBooks, and Macs. In order to beat the company at new contracts, Samsung will have to prove the cost-efficiency of its new 3-nanometer process.
Compatible with a variety of platforms
And it is looking like it may indeed be able to do so. Samsung has collaborated with German multinational Siemens to ensure their new chips work on a variety of platforms.
“Siemens EDA is pleased to have collaborated with Samsung to help ensure that our existing software platforms also work on Samsung’s new 3-nanometer process node since the initial development phase. Our longtime partnership with Samsung through the SAFE™ program generates significant value for our mutual customers, by certification of Siemens industry-leading EDA tools at 3nm,” said Joe Sawicki, Executive Vice President for the IC-EDA segment of Siemens Digital Industries Software.
Samsung’s chips will be manufactured in South Korea for now, first at its Hwaseong facilities before also moving to its Pyeongtaek center. The company also has plans for an upcoming chip plant to be set in Texas, which could eventually be able to produce 3-nanometer chips, but it is not scheduled to start mass manufacturing until 2024.
Recent massive global chip shortages have put a lot of pressure on chip manufacturers. Samsung’s new innovation could see some of that pressure reduced.
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